1) Field of the Invention
The present invention relates in general to methods for the formation of a device separation film among manufacturing processes for a semiconductor device and more particularly to methods for forming a field oxide fill in the semiconductor device.
2) Description of the Prior Art
The fabrication of an integrated circuit normally begins by processing the semiconductor substrate or wafer to divide the surface area into regions where active devices and substrate embedded interconnects are to be formed, and other regions of dielectric (e.g., field oxide regions) which electrically separate the active regions. The field oxide dielectric material is routinely silicon dioxide. Though various field oxide formation techniques have been developed and described, the technique commonly known as the localized oxidation of silicon (LOCOS) remains common therein the semiconductor industry. In the practice of LOCOS, the active regions of the silicon substrate are masked by a silicon nitride layer, while the field oxide regions are thermally oxidized to form a field dielectric region. Though fundamentally simple and efficient, the LOCOS process and its progeny, such as the Fully Recessed LOCOS (FUROX) and sidewall masked isolation (SWAMI) techniques, exhibit deficiencies which reduce yield or performance in the final semiconductor chip product.
A major problem with current field oxidation processes is that the field oxide is not planar (or coplanar) with the surrounding adjacent surface which causes problems in the overlying layers. Semiconductor devices require more levels of interconnects as component densities within the devices increase. A conventional LOCal Oxidation of Silicon (LOCOS) field isolation process may cause problems because the field isolation regions may have too much of a step height change that may make subsequent planarization steps required or more difficult.
LOCOS-type field isolation processes may cause additional problems when subsequently patterning a layer to form a gate electrode because reflective notching may occur. The changes in topography between a substrate and LOCOS-type of field isolation regions cause light to reflect and form notches in a masking layer pattern used to form a gate electrode. The mask pattern may have a feature with an uniform width, but the pattern formed in the masking layer by that mask may have a width that narrows near the edge of a field isolation region because of the reflective notching. The pattern in the masking layer is transferred to the conductive layer when the conductive layer is etched to form the gate electrode. This difference between the pattern of the mask and the gate electrode is undesired.
Other field isolation process have been developed that require etching a semiconductor substrate. There other processes, including trench isolation, semi-recessed or fully-recessed LOCOS processes, sidewall masked isolation (SWAMI) and the like, all require some type of substrate etch. Trenches in the substrate may not have uniform depths. Narrow trenches may not be formed to the same depth as wider trenches because the concentration of ions (of a plasma) is typically lowered for the narrower trench. Therefore, narrow trenches will be shallower than wider trenches. This effect is call "lag". Another problem with a substrate etch is that typically an endpoint does not exist. The depth of the substrate trench may be variable both across a substrate and between substrates in the same lot. A lack of control for the substrate etch poses step height problems for which no good solution exists.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 4,952,525 (Van der Plas) and U.S. Pat. No. 5,374,585 (Smith et al.). Van der Plas forms a FOX region that is thicker than the desired final thickness so that subsequent RIE etchings leave the FOX with the desired thickness. Smith uses the silicon nitride oxidation masking layer as a CMP stopping layer. However, Smith subjects the FOX to subsequent etches that can overetch the FOX and cause FOX integrity problem, especially around the edges to the FOX. However, the prior art processes can be further improved upon. Though a number to the prior art techniques attempt solve the non-planarity problem and usually provide relatively planar final concluding surfaces, the approaches can be improved upon.